MRF89XA-I/MQ【PDF 80/140 页】TXRX ISM SUB-GHZ ULP 32QFN

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MRF89XA

TABLE 3-10:

CONFIGURATION REGISTERS RELATED TO DATA PROCESSING IN BUFFERED

MODE

Register Name

DMODREG

FIFOCREG

FIFOCREG

FTXRXIREG

FTXRXIREG

FTXRXIREG

FTPRIREG

FTPRIREG

FTPRIREG

SYNCREG

SYNCREG

SYNCREG

SYNCV31REG

SYNCV23REG

SYNCV15REG

SYNCV07REG

Register Bits

DMODE0, DMODE1

FSIZE<1:0>

FTINT<5:0>

IRQ0RXS<1:0>

IRQ1RXS<1:0>

IRQ1TX

IRQ0TXST

FIFOFM

FIFOFSC

SYNCREN

SYNCWSZ<1:0>

SYNCTEN<1:0>

SYNCV<31:24>

SYNCV<23:16>

SYNCV<15:8>

SYNCV<7:0>

TX

X

X

X

—

—

X

X

—

—

—

—

—

—

—

—

—

RX

X

X

X

X

X

—

—

X

X

X

X

X

X

X

X

X

Description

Defines data operation mode ( Buffered)

Defines FIFO size

Defines FIFO threshold

Defines IRQ0 source in RX mode

Defines IRQ1 source in RX mode

Defines IRQ1 source in TX mode

Defines IRQ0 source in TX mode

Defines FIFO filling method

Controls FIFO filling status

Enables Sync word recognition

Defines Sync word size

Defines the error tolerance on Sync word recognition

Defines Sync word value

Defines Sync word value

Defines Sync word value

Defines Sync word value

TX Mode :

RX Mode:

1.

2.

3.

4.

5.

Program TX start condition and IRQs: Start TX

when FIFO is not empty (IRQ0TXST = 1 ) and

IRQ1 mapped to TXDONE (IRQ1TX = 1 ).

Go to TX mode (and wait for TX to be ready, see

Figure 5-3 ).

Write packet bytes into FIFO. TX starts when the

first byte is written (IRQ0TXST = 1 ).

Assumption: The FIFO is being filled through the

SPI Data faster than being unfilled by SR.

Wait for TXDONE interrupt (+ 1 bit period).

Go to Sleep mode.

1.

2.

3.

4.

Program RX/Stand-by interrupts: IRQ0 mapped

to FIFOEMPTY (IRQ0RXS<1:0> = 10 ) and

IRQ1 mapped to FIFO threshold

(IRQ1RXS<1:0> = 11 ). Configure FIFO thresh-

old to an appropriate value (for example, to

detect packet end, if its length is known).

Go to RX mode (note that RX is not ready imme-

diately, see Section 5.3.1, Optimized Receive

Cycle for more information).

Wait for FIFO threshold interrupt (i.e., Sync word

has been detected and FIFO has filled up to the

defined threshold).

If it is packet end, go to Stand-by (SR’s content

is lost).

5.

6.

Read packet byte from FIFO until FIFOEMPTY

goes low (or correct number of bytes is read).

Go to Sleep mode.

DS70622C-page 80

Preliminary

? 2010–2011 Microchip Technology Inc.

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